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complete, quad, 14/16-bit, high accuracy, serial input, bipolar voltage output dac i cmos tm preliminary technical data rev. pra 15-nov-04 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the prop erty of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2004 analog devices, inc. all rights reserved. features complete quad 14/16-bit d/a converter programmable output range: 10 v, 10.25 v, or 10.5 v 1 lsb max inl error, 1 lsb max dnl error low noise : 60 nv/ hz settling time: 10s max integrated reference buffers internal reference, 10 ppm/c on-chip temp sensor, 5c accuracy output control during power-up/brownout programmable short-circuit protection simultaneous updating via ldac asynchronous clr to zero code digital offset and gain adjust logic output control pins dsp/microcontroller compat ible serial interface temperature range:?40c to +85c i cmos? process technology applications industrial automation open/closed-loop servo control process control data acquisition systems automatic test equipment automotive test and measurement high accuracy instrumentation general description the AD5744/64 is a quad, 14/16-bit serial input, voltage output digital-to analog converter that operates from supply voltages of 12 v up to 15 v. nominal full-scale output range is 10 v, provided are integrated output amplifiers, reference buffers, internal reference, and proprietary power-up/power-down control circuitry. it also features a digital i/o port that may be programmed via the serial interface, and an analog temperature sensor. the part incorporates digital offset and gain adjust registers per channel. the AD5744/64 is a high performance converter that offers guaranteed monotonicity, integral nonlinearity (inl) of 1 lsb, low noise and 10 s settling time and includes an on-chip 5 v reference with a reference tempco of 10 ppm/c max. during power-up (when the supply voltages are changing), vout is clamped to 0v via a low impedance path. the AD5744/64 uses a serial interface that operates at clock rates of up to 30 mhz and is compatible with dsp and microcontroller interface standards. double buffering allows the simultaneous updating of all dacs. the input coding is programmable to either twos complement or offset binary formats. the asynchronous clear function clears all dac registers to either bipolar zero or zero-scale depending on the coding used. the AD5744/64 is ideal for both closed-loop servo control and open-loop control applications. the AD5744/64 is available in a 32-lead tqfp package, and offers guaranteed specifications over the ?40c to +85c industrial temperature range. see functional block diagram, figure 1. i cmos? process technology for analog systems designers within industrial/instrumentation eq uipment oems who need high performance ics at higher-voltage l evels, i cmos is a technology platform that enable s the development of analog ics capable of 30v an d operating at +/-15v supplies while allowing d ramatic reductions in power consumption and package size, and increased ac and dc performance. 4 .com u datasheet
preliminary technical data rev. pra 15-nov-04| page 2 of 27 table of contents functional block diagram .............................................................. 3 specifications..................................................................................... 4 ac performance characteristics ................................................ 6 timing characteristics ................................................................ 7 absolute maximum ratings.......................................................... 10 esd caution................................................................................ 10 pin configuration and function descriptions........................... 11 terminology .................................................................................... 13 typical performance characteristics ............................................. 15 general description ....................................................................... 16 dac architecture........................................................................... 16 reference buffers........................................................................ 16 serial interface ............................................................................ 16 simultaneous updating via ldac .......................................... 17 transfer function ......................................................................... 18 asynchronous clear ( clr )....................................................... 18 function register ....................................................................... 19 data register ............................................................................... 20 coarse gain register.................................................................... 20 fine gain register ........................................................................ 21 offset register............................................................................... 21 AD5744/64 features....................................................................... 22 analog output control ............................................................. 22 digital offset and gain control............................................... 22 programmable short-circuit protection................................. 22 digital i/o port........................................................................... 22 temperature sensor ................................................................... 22 local ground offset adjust......................................................... 22 applications information ............................................................... 23 typical operating circuit............................................................. 23 layout guidelines......................................................................... 24 isolated interface ........................................................................ 24 microprocessor interfacing ....................................................... 24 evaluation board ........................................................................ 26 outline dimensions ....................................................................... 27 ordering guide .......................................................................... 27 revision history revision pra 15-nov-04: preliminary version 4 .com u datasheet
preliminary technical data rev. pra 15-nov-04| page 3 of 27 functional block diagram input reg c gain reg c offset reg c dac reg c 14/16 dac c input reg d gain reg d reference buffers offset reg d dac reg d 14/16 dac d g1 g2 input reg b gain reg b offset reg b dac reg b 14/16 dac b input reg a gain reg a offset reg a dac reg a 14/16 14/16 dac a ldac vref cd temp rstin rstout vref ab refgnd agndd voutd agndc voutc agndb voutb agnda vouta iscc temp sensor reference buffers av ss sdin sclk sync sdo d0 d1 bin/2scomp clr av dd av ss av dd pgnd dv cc dgnd +5v reference voltage monitor and control input shift register and control logic g1 g2 g1 g2 g1 g2 refout figure 1. functional block diagram 4 .com u datasheet
preliminary technical data rev. pra 15-nov-04| page 4 of 27 specifications av dd = +11.4 v to +16.5 v, av ss = ?11.4 v to ?16.5 v, agnd = dgnd = refgnd = pgnd=0 v; refab = refcd= 5 v ext; dv cc = 2.7 v to 5.5 v, r load = 10 k, c l = 200 pf. all specifications t min to t max , unless otherwise noted. table 1. parameter a grade 1 b grade 1 c grade 1 unit test conditions/comments accurac resolution 1 14 1 14 1 14 bits ad54 ad544 relative accuracy in 4 2 1 sb ma differential nonlinearity 1 1 1 sb ma guaranteed monotonic bipolar zero error 1 1 1 mv ma at 25c. error at other temperatures obtained using bipolar ero tc. bipolar zero tc 2 2 2 ppm fsr/c ma zero code error 1 1 1 mv ma at 25c. error at other temperatures obtained using ero code tc. zero code tc 2 2 2 ppm fsr/c ma gain error .2 .2 .2 fsr ma at 25c. error at other temperatures obtained using gain tc. gain tc 2 2 2 ppm fsr/c ma dc crosstalk 2 .5 .5 .5 sb ma reference input/output reference input 2 reference input voltage 5 5 5 v nom 1 for specified performance dc input impedance 1 1 1 m min typically 1 m input current 1 1 1 a ma typically 3 na reference range 1/5 1/5 1/5 v min/ma reference output output voltage 4./5.1 4./ 5.1 4./5.1 v min/ma at 25c reference tc 1 1 1 ppm/c ma output noise.1 to 1 tbd tbd tbd v p-p typ noise spectral density tbd tbd tbd nv/ typ output caracteristics 2 output voltage range 3 1 1 1 v min/ma av dd /av ss 11.4 v 13 13 13 v min/ma av dd /av ss 1.5 v output voltage tc 2 2 2 ppm fsr/c ma output voltage drift v s time tbd tbd tbd ppm fsr/1 ours typ short circuit current 1 1 1 ma ma ri scc ? 4 .com u datasheet
preliminary technical data rev. pra 15-nov-04| page 5 of 27 parameter a grade 1 b grade 1 c grade 1 unit test conditions/comments v il , input low voltage 0.8 0.8 0.8 v max input current 10 10 10 a max total for all pins. t a = t min to t max . pin capacitance 10 10 10 pf max digital outputs (d0,d1, sdo) 2 output low voltage 0.4 0.4 0.4 v max dv cc = 5 v 10%, sinking 200 a output high voltage dv cc C 1 dv cc C 1 dv cc C 1 v min dv cc = 5 v 10%, sourcing 200 a output low voltage 0.4 0.4 0.4 v max dv cc = 2.7 v to 3.6 v, sinking 200 a output high voltage dv cc C 0.5 dv cc C 0.5 dv cc C 0.5 v min dv cc = 2.7 v to 3.6 v, sourcing 200 a high impedance leakage current 1 1 1 a max sdo only high impedance output capacitance 5 5 5 pf typ sdo only temp sensor accuracy 1 1 1 c typ at 25c 5 5 5 c max ?40c < t <+85c output voltage @ 25c 1.5 1.5 1.5 v typ output voltage scale factor 5 5 5 mv/c typ output voltage range 0/3.0 0/3.0 0/3.0 v min/max output load current 200 200 200 a max current source only. power on time 10 10 10 ms typ to within 5c power requirements av dd /av ss 11.4/16.5 11.4/16.5 11.4/16.5 v min/max dv cc 2.7/5.5 2.7/5.5 2.7/5.5 v min/max power supply sensitivity 4 ?v out /?v dd ?85 ?85 ?85 db typ ai dd 3.75 3.75 3.75 ma/channel max outputs unloaded ai ss 2.75 2.75 2.75 ma/channel max outputs unloaded di cc 1 1 1 ma max v ih = dv cc , v il = dgnd. tbd ma typ power dissipation 244 244 244 mw typ 12 v operation output unloaded 4 guaranteed by characterization. not production tested. 4 .com u datasheet
preliminary technical data rev. pra 15-nov-04| page 6 of 27 ac performance characteristics av dd = +11.4 v to +16.5 v, av ss = ?11.4 v to ?16.5 v, agnd = dgnd = refgnd = pgnd=0 v; refab = refcd= 5 v ext; dv cc = 2.7 v to 5.5 v, r load = 10 k?, c l = 200 pf. all specifications t min to t max , unless otherwise noted. guaranteed by design and characterization, not production tested. table 2. parameter a grade b grade c grade unit test conditions/comments dynamic performance output voltage settling time 8 8 8 s typ full-scale step 10 10 10 s max 1 1 1 s max 512 lsb step settling 16 bits slew rate 5 5 5 v/s typ digital-to-analog glitch energy 5 5 5 nv-s typ glitch impulse peak amplitude 5 5 5 mv max channel-to-channel isolation 100 100 100 db typ dac-to-dac crosstalk 5 5 5 nv-s typ digital crosstalk 5 5 nv-s typ digital feedthrough 1 1 nv-s typ effect of input bus activity on dac output under test output noise (0.1 hz to 10 hz) 0.1 0.1 lsb p-p typ output noise (0.1 khz to 100 khz) 5 45 45 v rms max 1/f corner frequency 1 1 khz typ output noise spectral density 60 60 nv/ hz typ measured at 10 khz complete system o utput noise spectral density 6 80 80 nv/ hz typ measured at 10 khz 5 guaranteed by design and characterization. not production tested. 6 includes noise contributions from integrated reference buffers, 14/16-bit dac and output amplifier. 4 .com u datasheet
preliminary technical data rev. pra 15-nov-04| page 7 of 27 timing characteristics av dd = +11.4 v to +16.5 v, av ss = ?11.4 v to ?16.5 v, agnd = dgnd = refgnd = pgnd = 0 v; refab = refcd= 5 v ext; dv cc = 2.7 v to 5.5 v, r load = 10 k?, c l = 200 pf. all specifications t min to t max , unless otherwise noted. table 3. parameter 7,8,9 limit at t min , t max unit description t 1 33 ns min sclk cycle time t 2 13 ns min sclk high time t 3 13 ns min sclk low time t 4 13 ns min sync falling edge to sclk falling edge setup time t 5 10 13 ns min 24 th sclk falling edge to sync rising edge t 6 40 ns min minimum sync high time t 7 5 ns min data setup time t 8 0 ns min data hold time t 9 20 ns min sync rising edge to ldac falling edge t 10 20 ns min ldac pulse width low t 11 5 ns min ldac falling edge to dac output response time t 12 10 s max dac output settling time t 13 20 ns min clr pulse width low t 14 12 s max clr pulse activation time t 15 11,12 20 ns max sclk rising edge to sdo valid t 16 12 8 ns min sclk falling edge to sync rising edge t 17 12 20 ns min sync rising edge to ldac falling edge 7 guaranteed by design and characterization. not production tested. 8 all input signals are specified with t r = t f = 5 ns (10% to 90% of dv cc ) and timed from a voltage level of 1.2 v. 9 see figure 2, figure 3, and figure 4. 10 stand-alone mode only. 11 measured with the load circuit of figure 5. 12 daisy-chain mode only. 4 .com u datasheet
preliminary technical data rev. pra 15-nov-04| page 8 of 27 db23 sclk sync sdin ldac v out ldac = 0 v out clr v out 12 24 db0 t 4 t 5 t 8 t 7 t 3 t 2 t 12 t 11 t 12 t 11 t 9 t 10 t 1 t 13 t 14 04641-pra-002 t 6 figure 2. serial interface timing diagram t 4 t 17 t 15 t 8 t 7 t 10 t 3 t 2 t 5 t 1 t 6 t 16 ldac sdo sdin sync sclk 24 48 db23 db0 db23 db0 db23 input word for dac n undefined input word for dac n+1 input word for dac n db0 0 4641-pra-003 figure 3. daisy chain timing diagram 4 .com u datasheet
preliminary technical data rev. pra 15-nov-04| page 9 of 27 sdo sdin sync sclk 24 48 db23 db0 db23 db0 db23 selected register data clocked out undefined nop condition input word specifies register to be read db0 04641-pra-005 figure 4. readback timing diagram 200 p ai ol 200 p ai oh v oh (min) or v ol (max) t o output pin c l 50pf 04641-pra-004 figure 5. load circuit for sdo timing diagram 4 .com u datasheet
preliminary technical data rev. pra 15-nov-04| page 10 of 27 absolute maximum ratings t a = 25c unless otherwise noted. transient currents of up to 100 ma will not cause scr latch-up. table 4. parameter rating av dd to agnd dgnd .3 v to 1 v av ss to agnd dgnd .3 v to 1 v dv cc to dgnd .3 v to v digital inputs to dgnd .3 v to dv cc .3 v digital outputs to dgnd .3 v to dv cc .3 v ref in to agnd prgnd .3 v to 1 v ref out to agnd av ss to av dd v out abcd to agnd av ss to av dd agnd to dgnd .3 v to .3 v operating temperature range industrial 4c to 5c storage temperature range 5c to 15c unction temperature t ma 15c 32-ead tfp package a thermal impedance tbdc/ reflow soldering peak temperature 22c time at peak temperature 1 sec to 4 sec stresses above those listed under absolute maimum ratings may cause permanent damage to the device. this is a stress rating only functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. eposure to absolute maimum rating conditions for etended periods may affect device reliability. esd caution esd electrostatic discharge sensitive device. electros tatic charges as high as 4 v readily accumulate on the human body and test euipment and can discharge wi thout detection. although this product features proprietary esd protection circuitry permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore proper esd precautions are recommended to avoid performance degradation or loss of functionality. 4 .com u datasheet
preliminary technical data rev. pra 15-nov-04| page 11 of 27 pin configuration and fu nction descriptions AD5744/64 top view (not to scale) sync sclk sdin sdo clr ldac d1 d0 agnda vouta voutb agndb agndc voutc voutd agndd rstout rstin dgnd dv cc av dd pgnd iscc av ss bin/2scomp av dd av ss temp refgnd refout refcd refab 1 32 25 916 8 24 17 pin 1 indicator figure 6. 32-lead tqfp pin configuration diagram table 5. pin function descriptions pin no. mnemonic function 1 sync active low input. this is the frame synchron ization signal for the serial interface. while sync is low, data is transferred in on the falling edge of sclk. 2 sclk 13 serial clock input. data is cl ocked into the shift register on the falling edge of sclk. this operates at clock speeds up to 30 mhz. 3 sdin 13 serial data input. data must be valid on the falling edge of sclk. 4 sdo serial data output. used to clock data from the serial register in daisy-chain or readback mode. 5 clr 13 active low input. asserting this pi n sets the dac registers to 0x0000. 6 ldac load dac. logic input. this is used to update the da c registers and consequently the analog output. when tied permanentl y low, the addressed dac register is updated on the 24 th clock of the serial register write. if ldac is held high during the write cycle, the dac input register is upda ted but the output is held off until the falling edge of ldac . in this mode, all analog outputs can be updated simultaneously on the falling edge of ldac . 7, 8 d0, d1 d0 and d1 form a digital i/o port. the user can configure these pins as inputs or outputs that are configurable and readab le over the serial interface. when configured as inputs, these pins have weak internal pull-ups to dv cc . 9 rstout reset logic output. this is the output from the on-chip vo ltage monitor used in the reset circuit. if desired, it may be us ed to control other system components. 10 rstin reset logic input. this inp ut allows external access to the internal reset logic. applying a logic 0 to this in put resets the dac output to 0 v. in normal operation, rstin should be tied to logic 1. 11 dgnd digital gnd pin. 12 dv cc digital supply pin. voltage ranges from 2.7 v to 5.5 v. when programmed as outputs, d0 and d1 are referenced to dv cc . 13, 31 av dd positive analog supply pins. voltag e ranges from 11.4 v to 16.5 v. 14 pgnd ground reference point for analog circuitry. 15, 30 av ss negative analog supply pins. voltage ranges from C11.4 v to C16.5 v. 13 internal pull-up device on this logic input. therefore, it can be left floating and will default to a logic high condition. 4 .com u datasheet
preliminary technical data re pra 15-no-4 page 1 o 7 pin no mnemonic function 16 iscc thi pin u ued in aociation ith an eternal reitor to agnd to program the hort-circuit current o the output ampliier 17 agndd ground reerence pin or dac d output ampliier 1 voutd analog output voltage o dac d buere d output ith a nominal ull-cale output range o 1 v the output ampliier i ca pale o directly driing a 1 , pf load 1 voutc analog output voltage o dac c buere d output ith a nominal ull-cale output range o 1 v the output ampliier i ca pale o directly driing a 1 , pf load agndc ground reerence pin or dac c output ampliier 1 agndb ground reerence pin or dac b output ampliier voutb analog output voltage o dac b buere d output ith a nominal ull-cale output range o 1 v the output ampliier i ca pale o directly driing a 1 , pf load vouta analog output voltage o dac a buere d output ith a nominal ull-cale output range o 1 v the output ampliier i ca pale o directly driing a 1 , pf load 4 agnda ground reerence pin or dac a output ampliier 5 refab eternal reerence voltage in put or channel a and b reerence input range i 1 v to 5 v program the ull-cale output oltage refin 5 v or peciied perormance 6 refcd eternal reerence voltage in put or channel c and d reerence input range i 1 v to 5 v program the ull-cale output oltage refin 5 v or peciied perormance 7 refout reerence output thi i the uered re erence output rom the internal oltage reerence the internal reerence i 5 v 1 mv, ith a reerence tempco o 1 ppm/c refgnd reerence ground return or the reerence generator and buer temp thi pin proide an output oltage pr oportional to temp erature the output oltage i 15 v typical at 5c ari ation ith temperature i 5 mv/c bin/ comp determine the dac coding hen et to a lo gic high, input coding i oet inary hen et to a logic lo, input coding i to complement see tale 6 and tale 7 4 .com u datasheet
preliminary technical data rev. pra 15-nov-04| page 13 of 27 terminology relative accuracy for the dac, relative accuracy or integral nonlinearity (inl) is a measure of the maximum deviation, in lsbs, from a straight line passing through the endpoints of the dac transfer function. a typical inl vs. code plot can be seen in figure ?. differential nonlinearity differential nonlinearity (dnl) is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed monotonic by design. a typical dnl vs. code plot can be seen in figures ?. monotonicity a dac is monotonic, if the output either increases or remains constant for increasing digital input code. the AD5744/64 is monotonic over its full operating temperature range bipolar zero error bipolar zero error is the deviation of the analog output from the ideal half-scale output of 0 v when the dac register is loaded with 0x8000 (offset binary coding) or 0x0000 (2scomplement coding) full-scale error full-scale error is a measure of the output error when full-scale code is loaded to the dac register. ideally the output voltage should be full scale value C 1 lsb. full-scale error is expressed in percentage of full-scale range. a plot of full-scale error vs. temperature can be seen in figure ?. negative full-scale error / zero scale error negative full-scale error is the error in the dac output voltage when 0x0000 (offset binary coding) or 0x8000 (2scomplement coding) is loaded to the dac register. ideally the output voltage should be negative full scale value C 1 lsb. output voltage settling time output voltage settling time is the amount of time it takes for the output to settle to a specified level for a full-scale input change. slew rate the slew rate of a device is a limatation in the rate of change of the output voltage. the output slewing speed of a voltage- output d/a converter is usually limited by the slew rate of the amplifier used at its output. slew rate is measured from 10% to 90% of the output signal and is given in v/s. gain error this is a measure of the span error of the dac. it is the deviation in slope of the dac transfer characteristic from the ideal, expressed as a percentage of the full-scale range. total unadjusted error total unadjusted error (tue) is a measure of the output error taking all the various errors into account. a typical tue vs. code plot can be seen in figure ?. zero-code error drift this is a measure of the change in zero-code error with a change in temperature. it is expressed in v/c. gain error drift this is a measure of the change in gain error with changes in temperature. it is expressed in (ppm of full-scale range)/c. digital-to-analog glitch impulse digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes state. it is normally specified as the area of the glitch in nv secs and is measured when the digital input code is changed by 1 lsb at the major carry transition (7fff hex to 8000 hex). see figure ?. digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of the dac from the digital inputs of the dac but is measured when the dac output is not updated. it is specified in nv secs and measured with a full-scale code change on the data bus, i.e., from all 0s to all 1s and vice versa. power supply sensitivity power supply sensitivity indicates how the output of the dac is affected by changes in the power supply voltage. dc crosstalk this is the dc change in the output level of one dac in response to a change in the output of another dac. it is measured with a full-scale output change on one dac while monitoring another dac. it is expressed in v. dac-to-dac crosstalk this is the glitch impulse transferred to the output of one dac due to a digital code change and subsequent output change of 4 .com u datasheet
preliminary technical data re pra 15-no-4 page 14 o 7 another dac thi include oth digital and analog crotal it i meaured y loading one o the dac ith a ull-cale code change all to all 1 and ice era ith ldac lo and monitoring the output o another dac the energy o the glitch i epreed in nv- channel-to-channel iolation thi i the ratio o the amplitude o the ignal at the output o one dac to a ine ae on the reerence input o another dac it i meaured in db 4 .com u datasheet
preliminary technical data rev. pra 15-nov-04| page 15 of 27 typical performance characteristics 4 .com u datasheet
preliminary technical data rev. pra 15-nov-04| page 16 of 27 general description the AD5744/64 is a quad 14/16-bit, serial input, bipolar voltage output dac. it operates from supply voltages of 11.4 v to 16.5 v and has a buffered output voltage of up to 10.5 v. data is written to the AD5744/64 in a 24-bit word format, via a 3-wire serial interface. the device also offers an sdo pin, which is available for daisy chaining or readback. the AD5744/64 incorporates a power-on reset circuit, which ensures that the dac registers power up loaded with 0x0000. the AD5744/64 also features a digital i/o port that may be programmed via the serial interface, an analog temperature sensor, on-chip 10 ppm/c voltage reference, on-chip reference buffers and per channel digital gain and offset registers. dac architecture the dac architecture of the AD5744/64 consists of a 14/16-bit current-mode segmented r-2r dac. the simplified circuit diagram for the dac section is shown in figure 13. the four msbs of the 14/16-bit data word are decoded to drive 15 switches, e1 to e15. each of these switches connects one of the 15 matched resistors to either agnd or iout. the remaining 12 bits of the data word drive switches s0 to s11 of the 12-bit r-2r ladder network. 2r e15 v ref 2r e14 e1 2r s11 rr r 2r s10 2r 12 bit r-2r ladder v out 2r s0 2r agnd r/8 4 msbs decoded into 15 equal segments figure 7. dac ladder structure reference buffers the AD5744/64 can operate with either an external or internal reference. the reference inputs (refab and refcd) have an input range up to 5 v. this input voltage is then used to provide a buffered positive and negative reference for the dac cores. the positive reference is given by + v ref 2 v ref while the negative reference to the dac cores is given by -v ref -2v ref these positive and negative reference voltages (along with the gain register values) define the output ranges of the dacs. serial interface the AD5744/64 is controlled over a versatile 3-wire serial interface that operates at clock rates of up to 30 mhz and is compatible with spi, spi, microwire and dsp standards. input shift register he input shift register is 24 bits ide data is loaded into the device ms first as a 24-bit ord under the control of a serial clock input sc he input register consists of a read/rite bit three register select bits three dac address bits and 14/16 data bits as shon in able 8he timing diagram for this operation is shon in igure 2 upon poer-up the dac registers are loaded ith ero code 0x0000 he corresponding output voltage depends on the state of the i/ 2scomp pin if the i/ 2scomp pin is tied to dd then the data coding is 2scomplement and the outputs ill poer-up to 0v if the i/ 2scomp pin is tied high then the data coding is offset binary and the outputs ill poer-up to egative ull-scale standalone operation he serial interface orks ith both a continuous and noncon- tinuous serial clock a continuous sc source can only be used if sc is held lo for the correct number of clock cycles in gated clock mode a burst clock containing the exact number of clock cycles must be used and sc must be taken high after the final clock to latch the data he first falling edge of sc starts the rite cycle xactly 24 falling clock edges must be applied to sc before sc is brought back high again if sc is brought high before the 24 th falling sc edge the rite is aborted if more than 24 falling sc edges are applied before sc is brought high the input data ill be corrupted he input register addressed is updated on the rising edge of sc in order for another serial transfer to take place sc must be brought lo again after the end of the serial data transfer data is automatically transferred from the input shift register to the input register of the addressed dac hen the data has been transferred into the input register of the addressed dac all dac registers and outputs can be updated by taking dac lo hile sc is high 4 .com u datasheet
preliminary technical data rev. pra 15-nov-04| page 17 of 27 68hc11* miso sync sdin sclk mosi sck pc7 pc6 ldac sdo sync sclk ldac sdo sync sclk ldac sdo sdin sdin *additional pins omitted for clarity AD5744/64* AD5744/64* AD5744/64* r figure 8. daisy chaining the AD5744/64 daisy-chain operation for systems that contain several devices, the sdo pin may be used to daisy-chain several devices together. this daisy-chain mode can be useful in system diagnostics and in reducing the number of serial interface lines. the first falling edge of sync starts the write cycle. the sclk is continuously applied to the input shift register when sync is low. if more than 24 clock pulses are applied, the data ripples out of the shift register and appears on the sdo line. this data is clocked out on the rising edge of sclk and is valid on the falling edge. by connecting the sdo of the first device to the din input of the next device in the chain, a multidevice interface is constructed. each device in the system requires 24 clock pulses. therefore, the total number of clock cycles must equal 24n, where n is the total number of AD5744/64s in the chain. when the serial transfer to all devices is complete, sync is taken high. this latches the input data in each device in the daisy chain and prevents any further data from being clocked into the input shift register. the serial clock may be a continuous or a gated clock. a continuous sclk source can only be used if sync is held low for the correct number of clock cycles. in gated clock mode, a burst clock containing the exact number of clock cycles must be used and sync must be taken high after the final clock to latch the data. readback operation readback mode is invoked by setting the r/ w bit = 1 in the serial input register write. with r/ w = 1, bits a2Ca0, in association with bits reg2 , reg1, and reg0, select the register to be read. the remaining data bits in the write sequence are dont cares. during the next spi write, the data appearing on the sdo output will contain the data from the previously addressed register. for a read of a single register, the nop command can be used in clocking out the data from the selected register on sdo. the readback diagram in figure 4 shows the readback sequence. for example, to read back the fine gain register of channel a on the AD5744/64, the following sequence should be implemented. first, write 0xa0xxxx to the AD5744/64 input register. this configures the AD5744/64 for read mode with the fine gain register of channel a selected. note that all the data bits, db15 to db0, are dont cares. follow this with a second write, a nop condition, 0x00xxxx. during this write, the data from the fine gain register is clocked out on the sdo line, i.e., data clocked out will contain the data from the fine gain register in bits db5 to db0. simultaneous updating via ldac after data has been transferred into the input register of the dacs, there are two ways in which the dac registers and dac outputs can be updated. depending on the status of both sync and ldac . individual dac updating in this mode, ldac is held low while data is being clocked into the input shift register. the addressed dac output is updated on the rising edge of sync . simultaneous updating of all dacs in this mode, ldac is held high while data is being clocked into the input shift register. all dac outputs are updated by taking ldac low any time after sync has been taken high. the update now occurs on the falling edge of ldac . 4 .com u datasheet
preliminary technical data re pra 15-no-4 page 1 o 7 v out dac register interface logic output i/v amplifier ldac sdo sdin 16-bit dac v refin sync input register sclk figure 9. simplified serial interface showing input loading circuitry for one dac channel transfer function table 6 and table 7 show the ideal input code to output voltage relationship for the AD5744/64 for both offset binary and twos complement data coding. table 6. ideal output voltage to input code relationship for the ad5764 digital input analog output offset binary data coding msb lsb v out 1111 1111 1111 1111 +2 v ref x (32767/32768) 1000 0000 0000 0001 +2 v ref x (1/32768) 1000 0000 0000 0000 0 v 0111 1111 1111 1111 -2 v ref x (1/32768) 0000 0000 0000 0000 -2 v ref x (32767/32768) twos complement data coding msb lsb v out 0111 1111 1111 1111 +2 v ref x (32767/32768) 0000 0000 0000 0001 +2 v ref x (1/32768) 0000 0000 0000 0000 0 v 1111 1111 1111 1111 -2 v ref x (1/32768) 1000 0000 0000 0000 -2 v ref x (32767/32768) table 7. ideal output voltage to input code relationship for the AD5744 digital input analog output offset binary data coding msb lsb v out 11 1111 1111 1111 +2 v ref x (8192/8192) 10 0000 0000 0001 +2 v ref x (1/8192) 10 0000 0000 0000 0 v 01 1111 1111 1111 -2 v ref x (1/8192) 00 0000 0000 0000 -2 v ref x (8192/8192) twos complement data coding msb lsb v out 01 1111 1111 1111 +2 v ref x (8192/8192) 00 0000 0000 0001 +2 v ref x (1/8192) 00 0000 0000 0000 0 v 11 1111 1111 1111 -2 v ref x (1/8192) 10 0000 0000 0000 -2 v ref x (8192/8192) the output voltage expression for the ad5764 is given by: ? ? ? ? ? ? + ? = ? ? ? ? ? ? + ? = 4 .com u datasheet
preliminary technical data rev. pra 15-nov-04| page 19 of 27 table 8. AD5744/64 input register format msb lsb db23 db22 db21 db20 db19 db18 db17 db16 db15 db14 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 r/ w 0 reg2 reg1 reg0 a2 a1 a0 data table 9. input register bit functions r/ w indicates a read from or a write to the addressed register. reg2, reg1, reg0 used in association with the address bits to determine if a read or write opera tion is to the data register, offset register, gain register, or function register. reg2 reg1 reg0 function 0 0 0 function register 0 1 0 data register 0 1 1 coarse gain register 1 0 0 fine gain register 1 0 1 offset register a2, a1, a0 these bits are used to decode the dac channels a2 a1 a0 channel address 0 0 0 dac a 0 0 1 dac b 0 1 0 dac c 0 1 1 dac d 1 0 0 all dacs d15 C d0 data bits function register the function register is addressed by setting the three reg bits to 000. the values written to the address bits and the data bi ts determine the function addressed. the functions available through the function register are shown in table 10 and table 11. table 10. function register options reg2 reg1 reg0 a2 a1 a0 db15 .. db6 db5 db4 db3 db2 db1 db0 0 0 0 0 0 0 nop, data = dont care 0 0 0 0 0 1 dont care local- ground- offset adjust d1 direction d1 value d0 direction d0 value sdo disable 0 0 0 1 0 0 clr, data = dont care 0 0 0 1 0 1 load, data = dont care 4 .com u datasheet
preliminary technical data re pra 15-no-4 page o 7 tale 11 eplanation o function regiter option nop no operation intruction u ed in readac operation local-ground- oet adut set y the uer to enale loca l-ground-oet adut unction cleared y the uer to diale local-gr ound-oet adut unction deault d / d1 direction set y the uer to enale d/d1 a output cleared y the uer to enale d/d1 a in put deault hae ea internal pull-up d / d1 value i/o port tatu it logic alue ritte n to thee location determine the logic output on the d and d1 pin hen conigured a output thee it indicate the tatu o the d and d1 pin hen the i/o port i actie a an input hen enaled a input, thee it are do nt care during a rite operation sdo diale set y the uer to diale the sdo output cleared y the uer to ena le the sdo output deault clr addreing thi unction reet the da c output to v in to complement mode and negatie ull cale in inary mode load addreing thi unction update the dac regiter and coneuently the analog output data register the data regiter i addreed y etting the three reg it to 1 the dac addre it elect ith hich dac channel the dat a traner i to tae place reer to tale the data it are in poition d15 to d or the ad5764 a hon in tale 1 and d1 to d or the AD5744 a hon in tale 1 tale 1 programming the ad5764 data regiter reg reg1 reg a a1 a db15 db14 db1 db1 db 11 db1 db db db7 db6 db 5 db4 db db db1 db 1 dac addre 16 bit dac data tale 1 programming the AD5744 data regiter reg reg1 reg a a1 a db15 db14 db1 db1 db 11 db1 db db db7 db6 db 5 db4 db db db1 db 1 dac addre 14 bit dac data x x coarse gain register the coare gain regiter i addreed y etting the three reg it to 11 the dac addre it elect ith hich dac channel the data traner i to tae place reer to tale the coare gain regiter i a -it regiter and allo the uer to elect t he output range o each dac a hon in tale 15 tale 14 programming the coare gain regiter reg reg1 reg a a1 a db15 db db1 db 1 1 dac addre dont care cg1 cg tale 15 output range selection output range cg1 cg 1 v 15 v 1 15 v 1 4 .com u datasheet
preliminary technical data rev. pra 15-nov-04| page 21 of 27 fine gain register the fine gain register is addressed by setting the three reg bi ts to 100. the dac address bits select with which dac channel th e data transfer is to take place (refer to table 9). the fine gain register is a 6-bit register and allows the user to adjust the gain of each dac channel by -32 lsbs to +31 lsbs in 1 lsb steps as shown in table 16 and table 17. table 16. programming ad5764 fine gain register reg2 reg1 reg0 a2 a1 a0 db15 . db6 db5 db4 db3 db2 db1 db0 1 0 0 dac address dont care fg5 fg4 fg3 fg2 fg1 fg0 table 17. fine gain register options gain adjustment fg5 fg4 fg3 fg2 fg1 fg0 +31 lsbs 0 1 1 1 1 1 +30 lsbs 0 1 1 1 1 0 - - - - - - no adjustment 0 0 0 0 0 0 - - - - - - -31 lsbs 1 0 0 0 0 1 -32 lsbs 1 0 0 0 0 0 offset register the offset register is addressed by setting the three reg bits to 101. the dac address bits select with which dac channel the d ata transfer is to take place (refer to table 9). the offset register is an 8-bit register and allows the user to adjust the offset of each channel by C 15.875 lsbs to + 16 lsbs in steps of 1/8 lsb as shown in table 18 and table 19. table 18. programming the offset register reg2 reg1 reg0 a2 a1 a0 db15 . db8 db7 db6 db5 db4 db3 db2 db1 db0 1 0 1 dac address dont care of7 of6 of5 of4 of3 of2 of1 of0 table 19. offset register options offset adjustment of7 of6 of5 of4 of3 of2 of1 of0 +15.875 lsbs 0 1 1 1 1 1 1 1 +16.5 lsbs 0 1 1 1 1 1 1 0 - - - - - - - - no adjustment 0 0 0 0 0 0 0 0 - - - - - - - - -15.875 lsbs 1 0 0 0 0 0 0 1 -16 lsbs 1 0 0 0 0 0 0 0 4 .com u datasheet
preliminary technical data re pra 15-no-4 page o 7 AD5744/64 features analog output control in many indutrial proce control application, it i ital that the output oltage e controlled during poer up and during ronout condition hen the upply oltage are changing, the vout pin i clamped to v ia a lo impedance path to preent the output amp eing horted to v during thi time, tranmiion gate g1 i alo opened thee condition are maintained until the poer upplie tailie and a alid ord i ritten to the dac regiter at thi time, g open and g1 cloe both tranmiion gate are alo eternally controllale ia the reet in rstin control input for intance, i rstin i drien rom a attery uperior chip, the rstin input i drien lo to open g1 and cloe g on poer-o or during a ronout conerely, the on-chip oltage detector output rstout i alo aailale to the uer to control other part o the ytem the aic tranmiion gate unctionality i hon in figure 1 voltage monitor and control agnda vouta g1 rstout rstin g 4641-pra- figure 1 analog output control circuitry digital offset and gain control the AD5744/64 incorporate a digital oet adut unction ith a 16 lsb adut range and 15 lsb reolution the gain regiter allo the uer to adut the AD5744/64 ull-cale output range the ull-cale output can e programmed to achiee ull-cale range o 1 v, 15 v, and 15 v a ine gain trim i alo aailale, alloing a trim range o 16 lsb in 1 lsb tep programmable short-circuit protection the hort-circuit current o the output ampliier can e pro- grammed y inerting an eternal reitor eteen the iscc pin and agnd the programmale range or the current i 5 a to 1 ma, correponding to a reitor range o 1 ? ? = 4 .com u datasheet
preliminary technical data rev. pra 15-nov-04| page 23 of 27 applications information typical operating circuit figure 11 shows the typical operating circuit for the AD5744/64. the only external components needed for this precision 14/16-bit dac are decoupling capacitors on the supply pins, r-c connection from refout to refab and refcd and a short circuit current setting resistor. because the device incorporates a voltage reference, and reference buffers, it eliminates the need for an external bipolar reference and associated buffers. this leads to an overall saving in both cost and board space. in the circuit below, vdd and vss are both connected to 15 v, but vdd and vss can operate with supplies from 11.4 v to 16.5 v. in figure 11, agnda is connected to refgnd, but the option of force/sense is included on this device, if required by the user. 1 2 3 4 5 6 7 8 23 22 21 18 19 20 24 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 AD5744/64 sync sclk sdin sdo d0 ldac clr d1 vouta voutb agndb voutd voutc agndc agnda agndd rstout rstin dgnd dvcc avdd pgnd avss iscc bin/2scomp avdd avss temp refgnd refout refcd refab sync sclk sdin sdo ldac d0 d1 rstout rstin bin/2scomp +5v +5v +15v -15v +15v -15v vouta v outb v outc v outd 6k : 100 nf 100 nf 100 nf 10 f 10 f 10 f 100 nf 100 nf 10 f 10 f 10 f 3k : temp figure 11. typical operating circuit precision voltage reference selection to achieve the optimum performance from the AD5744/64 over its full operating temperature range an external voltage reference must be used. thought should be given to the selection of a precision voltage reference. the AD5744/64 has two reference inputs, refab and refcd. the voltages applied to the reference inputs are used tomprovide a buffered positiver and negative reference for the dac cores. therefore, any error in the voltage reference is reflected in the outputs of the device. there are four possible sources of error to consider when choosing a voltage reference for high accuracy applications: initial accuracy, temperature coefficient of the output voltage, long term drift and output voltage noise. initial accuracy error on the output voltage of an external reference could lead to a full-scale error in the dac. therefore, to minimize these errors, a reference with low initial accuracy error specification is preferred. also, choosing a reference with an output trim adjustment, such as the adr425, allows a system designer to trim system errors out by setting the reference voltage to a voltage other than the nominal. the trim adjustment can also be used at temperature to trim out any error. long term drift is a measure of how much the reference output voltage drifts over time. a reference with a tight lon-term drift specification ensures that the overall solution remains relatively stable over its entire lifetime. the temperature coefficient of a references output voltage affects inl, dnl and tue. a reference with a tight tempaerature coefficient specifiaction should be chosen to reduce the dependence of the dac output voltage on ambient conditions. in high accuracy applications, which have a relatively low noise budget, reference output voltage noise needs to be considered. choosing a reference waith as low an output noise voltage as practical for the system resolution required is important. precision voltage references such as the adr435 (xfet design) produce low output noise in the 0.1 hx to 10 hz region. however, as the circuit bandwidth increases, filtering the output of the reference may be required to minimise the output noise. table 20. partial list of precision references recommended for use with the AD5744/64 part no. initial accuracy (mv max) long-term drift (ppm typ) temp drift (ppm/ c max) 0.1 hz to 10 hz noise (v p-p typ) adr435 6 30 3 3.4 adr425 6 50 3 3.4 adr02 5 50 3 15 adr395 6 50 25 5 ad586 2.5 15 10 4 4 .com u datasheet
preliminary technical data rev. pra 15-nov-04| page 24 of 27 layout guidelines in any circuit where accura cy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. the printed circuit board on which the AD5744/64 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of th e board. if the AD5744/64 is in a system where multiple devices require an agnd-to-dgnd connection, the connection should be made at one point only. the star ground point should be established as close as possible to the device. the AD5744/64 should have ample supply bypassing of 10 f in parallel with 0.1 f on each su pply located as close to the package as possible, ideally right up against the device. the 10 f capacitors are the tantalum bead type. the 0.1 f capacitor should have low effective seri es resistance (esr) and low effective series inductance (esi) such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. the power supply lines of the AD5744/64 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. a ground line routed between the sdin and sclk lines helps reduce crosstalk between them (not required on a multilayer board, which has a separate ground plane, but sepa rating the lines helps). it is essential to minimize noise on the reference inputs, because it couples through to the dac output. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feed through the board. a microstrip technique is by far the best, but not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground plane, while signal traces are placed on the solder side. isolated interface in many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled. opto-isolators can provide voltage isolation in excess of 3 kv. the serial loading structure of the AD5744/64 makes it ideal for opto-isolated interfaces, because the number of interface lines is kept to a minimum. figure 12 shows a 4- channel isolated interface to the AD5744/64. to reduce the number of opto-isolators, if the simultaneous updating of the dac is not required, the ldac pin may be tied permanently low. the dac can then be updated on the rising edge of sync. dv cc to sdin to sclk to sync sync out serial clock out serial data out controller opto-coupler to ldac control out figure 12. isolated interface microprocessor interfacing microprocessor interfacing to th e AD5744/64 is via a serial bus that uses standard protocol compatible with microcontrollers and dsp processors. the communications channel is a 3-wire (minimum) interface consisting of a clock signal, a data signal, and a synchroni zation signal. the AD5744/64 requires a 24-bit data word with data valid on the falling edge of sclk. for all the interfaces, the dac output update may be done automatically when all the data is clocked in, or it may be done under the control of ldac. the contents of the dac register may be read using the readback function. AD5744/64 to mc68hc11 interface figure 13 shows an example of a serial interface between the AD5744/64 and the mc68hc11 microcontroller. the serial peripheral interface (spi) on the mc68hc11 is configured for master mode (mstr = 1), clock polarity bit (cpol = 0), and the clock phase bit (cpha = 1). the spi is configured by w r i t i n g t o t h e s p i c o n t r o l r e g i s t e r ( s p c r ) ---- -see the 68hc11 user manual . sck of the 68hc11 drives the sclk of the AD5744/64, the mosi output drives the serial data line (din) of the AD5744/64, and the miso input is driven from sdo. the sync is driven from one of the port lines, in this case pc7. when data is being transmi tted to the AD5744/64, the sync line 4 .com u datasheet
preliminary technical data rev. pra 15-nov-04| page 25 of 27 (pc7) is taken low and data is transmitted msb first. data appearing on the mosi output is valid on the falling edge of sck. eight falling clock edges occur in the transmit cycle, so, in order to load the required 24-bit word, pc7 is not brought high until the third 8-bit word has been transferred to the dacs input shift register. AD5744/64* sclk sdin sync mosi sclk pc7 mc68hc11* *additional pins omitted for clarity sdo miso figure 13. AD5744/64 to mc68hc11 interface ldac is controlled by the pc6 port output. the dac can be updated after each 3-byte transfer by bringing ldac low. this example does not show other serial lines for the dac. if clr were used, it could be controlled by port output pc5, for example. AD5744/64 to 8051 interface the AD5744/64 requires a clock synchronized to the serial data. for this reason, the 8051 must be operated in mode 0. in this mode, serial data enters and exits through rxd, and a shift clock is output on txd. p3.3 and p3.4 are bit programmable pins on the serial port and are used to drive sync and ldac, respectively. the 8051 provides the lsb of its sbuf register as the first bit in the data stream. the user must ensure that the data in the sbuf register is arranged correctly , because the dac expects msb first. when data is to be transmitted to the dac, p3.3 is taken low. data on rxd is clocked out of the microcontroller on the rising edge of txd and is valid on the falling edge. as a result, no glue logic is required between this dac and the microcontroller interface. the 8051 transmits data in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. because the dac expects a 24-bit word, sync (p3.3) must be left low after the first eight bits are transferred. after the third byte has been transferred, the p3.3 line is taken high. the dac may be updated using ldac via p3.4 of the 8051. AD5744/64 to adsp2101/adsp2103 interface an interface between the AD5744/64 and the adsp2101/ adsp2103 is shown in figure 14. the adsp2101/adsp2103 should be set up to operate in the sport transmit alternate framing mode. the adsp2101 /adsp2103 are programmed through the sport control regist er and should be configured as follows: internal clock operation, active low framing, and 24-bit word length. transmission is initiated by writing a word to the tx register after the sport has been enabled. as the data is clocked out of the dsp on the rising edge of sclk, no glue logic is required to interface the dsp to the dac. in the interface shown, the dac output is updated using the ldac pin via the dsp. alternatively, the ldac input could be tied permanently low, and then the update takes place automatically when tfs is taken high. AD5744/64* sclk sdin sync dt sclk rfs adsp2101/ adsp2103* *additional pins omitted for clarity sdo dr tfs ldac fo figure 14. AD5744/64 to adsp2101/adsp2103 interface AD5744/64 to pic16c6x/7x interface the pic16c6x/7x synchronous serial port (ssp) is configured as an spi master with the clock polarity bit set to 0. this is done by writing to the synchronous serial port control register (sspcon). see the pic16/17 microcontroller user manual . in this example, i/o port ra1 is being used to pulse sync and enable the serial port of th e AD5744/64. this microcontroller transfers only eight bits of data during each serial transfer operation; therefore, three co nsecutive write operations are needed. figure 15 shows the connection diagram. AD5744/64* sclk sdin sync sdo/rc5 sclk/rc3 ra1 pic16c6x/7x* *additional pins omitted for clarity sdo sdi/rc4 figure 15. AD5744/64 to pic16c6x/7x interface 4 .com u datasheet
preliminary technical data re pra 15-no-4 page 6 o 7 evaluation board the AD5744/64 come ith a u ll ealuation oard to aid deigner in ealuating the high perormance o the part ith a minimum o eort all that i reuired ith the ealuation oard i a poer upply, and a pc the AD5744/64 ealuation it include a populated, te ted AD5744/64 printed circuit oard the ealuation oard inte race to the usb interace o the pc sotare i aailale ith the ealuation oard, hich allo the uer to eaily prog ram the AD5744/64 the otare run on any pc that ha mi croot indo //nt/xp intalled an application note is available that gives full details on operating the evaluation board. 4 .com u datasheet
preliminary technical data rev. pra 15-nov-04| page 27 of 27 outline dimensions top view (pins down) 1 24 17 25 32 8 9 16 0.45 0.37 0.30 0.80 bsc 7.00 sq 9.00 sq 1.05 1.00 0.95 seating plane 1.20 max 0.15 0.05 7 0 0.75 0.60 0.45 compliant to jedec standards ms-026aba figure 16. 32-lead thin quad flatpack [tqfp] (su-32) dimensions shown in millimeters ordering guide model function inl package description package option ad5764csu quad 16-bit dac 1 lsb max 32-lead tqfp su-32 ad5764bsu quad 16-bit dac 2 lsb max 32-lead tqfp su-32 ad5764asu quad 16-bit dac 4 lsb max 32-lead tqfp su-32 AD5744csu quad 14-bit dac 1 lsb max 32-lead tqfp su-32 AD5744bsu quad 14-bit dac 2 lsb max 32-lead tqfp su-32 AD5744asu quad 14-bit dac 4 lsb max 32-lead tqfp su-32 ? 2004 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. 4 .com u datasheet

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